D765 Ver la hoja de datos (PDF) - NEC => Renesas Technology
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D765 Datasheet PDF : 17 Pages
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NEC
uPD765A/uPD765B
liming Waveforms (Cont)
Write Clock
Index
I
INDEX
Internal Registers
The uPD765A/uPD765B
contains two registers which
may be accessed by the main system processor: a sta-
tus register and a data register. The 8-bit main status
register contains the status information of the FDC, and
may be accessed at any time. The 8-bit data register
(which actually consists of four registers, STO-ST3, in a
stack with only one register presented to the data bus at
a time), stores data, commands, parameters, and FDD
status information. Data bytes are read out of, or written
into, the data register in order to program or obtain the
results after a particular command (table 3). Only the
status register may be read and used to facilitate the
transfer of data between the processor and uPD765A/
uPD765B.
The relationship between the status/data registers and
the signals RD, WR, and A0 is shown in table 1.
Table 1. Status/Data Register Addressing
A0
RD
WR
Function
0
0
1 Read main status register
0
1
0 Illegal
0
0
0 Illegal
1
0
0 Illegal
1
0
1 Read from data register
1
1
0 Write into data register
Table 2. Main Status Register
No.
DB0
DB1
DB2
DB3
DB4
DB5
D B 6
DB7
Name
Function
D0B
(FDD 0 Busy)
FDD number 0 is in the seek mode. II any
of the DnB bits IS set FDC will not accept
read or write command.
D1B
(FDD 1 Busy)
FDD number1 is in the seek mode. If any of
the DnB bits IS set FDC will not accept read
or write command.
D2B
(FDD 2 Busy)
FDD number 2 is in the seek mode If any
of the DnB bits IS set FDC will not acceot
read or write command
D3B
(FDD 3 Busy)
FDD number 3 is in the seek mode. If any
of the DnB bits IS set FDC will not accept
read or write command
CB
(FDC Busy)
A Read or Write command is in orocess.
FDC will not accept any other command.
EXM
(Execution Mode)
This bit is set only during execution ohase
in non-DMA mode When DB5 goes low,
execution phase has ended and result
phase has started. It operates only during
non-DMA mode of operation
DIO
Indicates direction of data transfer be-
(Data Input/Output) tween FDC and data regrster If DIO=1,
then transfer is from data register to the
processor. If DIO = 0, then transfer is from
the processor to data register.
RQM
(Request for Master)
Indicates data register IS ready to send or
receive data to or from the processor Both
bits DIO and RQM should be used to per-
form the hand-shaking functions of
“ready” and “directron” to the processor
The DIO and RQM bits in the status register indicate
when data is ready and in which direction data will be
transferred on the data bus. See figure 1.
Figure 1. DIO and RQM
Data In/Out
(DIO)
Out FDC and Into Processor
Out Processor and Into FDC
II
C
The bits in the main status register are defined in
table 2.
5-l 1
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