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DM9102

10/100Mbps Single Chip LAN Controller

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DM9102

10/100Mbps Single Chip LAN Controller

Configuration Register Structure

Device ID

Vendor ID

00H

Status (with bit 4 set to 1)

Command

04H

Class Code = 020000h

Revision

08H

BIST

Header Type

Latency Timer Cach Line Size 0CH

Bass Address Register CBIO

10H

Bass Address Register CBMA

14H

18H

1CH

Reserved

20H

24H

28H

Subsystem ID

Subsystem Vendor ID

2CH

Expansion ROM Base Address

30H

Reserved

Reserved

Cap_Ptr

34H

38H

Max_Lat

Min_Gnt

Interrupt Pin = 1 Interrupt Line 3CH

Device Specific Configuration Register

40H

44H

Reserved

48H

4CH

Key to Default

In the register description that follows, the default

' column takes the form <Reset Value>

Where

<Reset Value>:

1 Bit set to logic one

0 Bit set to logic zero

X No default value

<Access Type>:

RO = Read only

RW = Read/Write

R/C : means Read / Write & Write "1" for Clear.

Final

13

Version: DM9102-DS-F3

August 30, 2000

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