DM9102 Ver la hoja de datos (PDF) - Unspecified
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DM9102 Datasheet PDF : 63 Pages
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DM9102
10/100Mbps Single Chip LAN Controller
Bit
31:24
23:16
15:8
Default
00h
00h
00h
7:0
00h
Type
RO
RO
RW
RO
Description
Built-In-Self Test (=00h Means No Implementation)
Header Type (= 00h Means single function with Predefined Header Type )
Latency Timer For The Bus Master.
The latency timer is guaranteed by the system and measured by clock
cycles. When the FRAME# asserted at the beginning of a master period by
the DM9102, the value will be copied into a counter and start counting
down. If the FRAME# is de-asserted prior to count expiration, this value is
meaningless. When the count expires before GNT# is de-asserted, the
master transaction will be terminated as soon as the GNT# is removed.
While GNT# signal is removed and the counter is non-ZERO, the DM9102
will continue with its data transfers until the count expires. The system host
will read MIN_GNT and MAX_LAT registers to determine the latency
requirement for the device and then initialize the latency timer with an
appropriate value.
Cache-line Size For Memory Read Mode Selection (00h Means No
Implementation For Use)
I/O Base Address (Xxxxxx10 - PCIIO)
31
I/O Base Address
I/O Base Address
PCI I/O Range Indication
I/O or Memory Space Indicator
76
000000
10
1
Bit
Default
31:7 Undefined
6:1 000000b
0
1b
Type
RW
RO
RO
Description
PCI I/O Base Address
This is the base address value for I/O access cycles. It will be compared to
AD[31:7] in the address phase of bus command cycle for the I/O resource
access.
PCI I/O Range Indication
It indicates that the minimum I/O resource size is 80h.
I/O Space Or Memory Space Base Indicator
Determines that the register maps into the I/O space.(=1 Indicates I/O
Base)
Memory Mapped Base Address (Xxxxxx14 - PCIMEM)
31
Memory Mapped
Base
Memory Base Address
Memory Range Indication
I/O or Memory Space Indicator
76
000000
10
0
18
Final
Version: DM9102-DS-F03
August 30, 2000
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