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DM9000B

Ethernet Controller With General Processor Interface

Davicom Semiconductor, Inc. 

DM9000B

Ethernet Controller with General Processor Interface

5. Pin Description

I = Input

O = Output

I/O = Input/Output O/D = Open Drain P = Power

# = asserted low

PD = internal pull-low about 60K

5.1 Processor Interface

Pin No. Pin Name

35

IOR#

36

IOW#

37

CS#

32

CMD

34

INT

18,17,16,

14,13,12,

11,10

31,29,28,

27,26,25,

24,22

SD0~7

SD8~15

Type

Description

Processor Read Command

I,PD This pin is low active at default, its polarity can be modified by EEPROM

setting. See the EEPROM content description for detail

Processor Write Command

I,PD This pin is low active at default, its polarity can be modified by EEPROM

setting. See the EEPROM content description for detail

Chip Select

I,PD

A default low active signal used to select the DM9000B. Its polarity can be

modified by EEPROM setting. See the EEPROM content description for

detail.

Command Type

I,PD When high, the access of this command cycle is DATA port

When low, the access of this command cycle is INDEX port

Interrupt Request

O,PD

This pin is high active at default, its polarity can be modified by EEPROM

setting or by strap pin EECK. See the EEPROM content description for

detail

Processor Data Bus bit 0~7

I/O,PD

Processor Data Bus bit 8~15

I/O,PD

In 16-bit mode, these pins act as the processor data bus bit 8~15;

When EECS pin is pulled high , they have other definitions. See 8-bit

mode pin description for details.

5.1.1 8-bit mode pins

Pin No. Pin Name

22

WAKE

24

LED3

25,26,27

GP6~4

Final

Version: DM9000B-13-DS-F02

June 4, 2009

Type

Description

O,PD Issue a wake up signal when wake up event happens

O,PD

O,PD

Full-duplex LED

In LED mode 1, Its low output indicates that the internal PHY is operated

in full-duplex mode, or it is floating for the half-duplex mode of the internal

PHY

In LED mode 0, Its low output indicates that the internal PHY is operated

in 10M mode, or it is floating for the 100M mode of the internal PHY

Note: LED mode is defined in EEPROM setting.

General Purpose output pins:

These pins are output only for general purpose that is configured by

register 1Fh.

GP6 pin also act as trap pin for the INT output type.

When GP6 is pulled high, the INT is Open-Drain output type;

Otherwise it is force output type.

10

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