DM9000B Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.
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DM9000B Datasheet PDF : 56 Pages
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DM9000B
Ethernet Controller with General Processor Interface
8.1 Basic Mode Control Register (BMCR) - 00 ................................................................................................. 28
8.2 Basic Mode Status Register (BMSR) - 01................................................................................................... 29
8.3 PHY ID Identifier Register #1 (PHYID1) - 02 .............................................................................................. 30
8.4 PHY ID Identifier Register #2 (PHYID2) - 03 .............................................................................................. 30
8.5 Auto-negotiation Advertisement Register (ANAR) - 04 ............................................................................... 31
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05 ................................................................... 32
8.7 Auto-negotiation Expansion Register (ANER)- 06 ...................................................................................... 32
8.8 DAVICOM Specified Configuration Register (DSCR) - 16.......................................................................... 33
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17 ..................................................... 34
8.10 10BASE-T Configuration/Status (10BTCSR) - 18..................................................................................... 35
8.11 Power down Control Register (PWDOR) - 19 ........................................................................................... 36
8.12 (Specified config) Register – 20 ................................................................................................................ 36
9. Functional Description .................................................................................................... 38
9.1 Host Interface .............................................................................................................................................. 38
9.2 Direct Memory Access Control.................................................................................................................... 38
9.3 Packet Transmission ................................................................................................................................... 38
9.4 Packet Reception ........................................................................................................................................ 38
9.5 100Base-TX Operation ............................................................................................................................... 39
9.5.1 4B5B Encoder...................................................................................................................................... 39
9.5.2 Scrambler............................................................................................................................................. 39
9.5.3 Parallel to Serial Converter.................................................................................................................. 39
9.5.4 NRZ to NRZI Encoder.......................................................................................................................... 39
9.5.5 MLT-3 Converter .................................................................................................................................. 39
9.5.6 MLT-3 Driver ........................................................................................................................................ 39
9.5.7 4B5B Code Group ............................................................................................................................... 40
9.6 100Base-TX Receiver ................................................................................................................................. 41
9.6.1 Signal Detect........................................................................................................................................ 41
9.6.2 Adaptive Equalization .......................................................................................................................... 41
9.6.3 MLT-3 to NRZI Decoder ....................................................................................................................... 41
9.6.4 Clock Recovery Module....................................................................................................................... 41
9.6.5 NRZI to NRZ ........................................................................................................................................ 41
9.6.6 Serial to Parallel................................................................................................................................... 41
9.6.7 Descrambler......................................................................................................................................... 41
9.6.8 Code Group Alignment ........................................................................................................................ 42
9.6.9 4B5B Decoder...................................................................................................................................... 42
9.7 10Base-T Operation .................................................................................................................................... 42
9.8 Collision Detection ...................................................................................................................................... 42
9.9 Carrier Sense .............................................................................................................................................. 42
9.10 Auto-Negotiation........................................................................................................................................ 42
9.11 Power Reduced Mode............................................................................................................................... 43
Final
4
Version: DM9000B-13-DS-F02
June 4, 2009
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