DM9000 Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.

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Lista de partido

DM9000

ISA to Ethernet MAC Controller with Integrated 10/100 PHY

Davicom Semiconductor, Inc. 

68,69,70,

71

GPIO0~3

78

LINK_O

79

WAKEUP

80

PW_RST#

24,74,75,

NC

77

5.8 Power Pins

5,20,36,

DVDD

55,72,90,

73

15,23,42,

DGND

58,63,81,

99,76

DM9000

ISA to Ethernet MAC Controller with Integrated 10/100 PHY

I/O General I/O Ports

Registers GPCR and GPR can program these pins

The GPIO0 is an output mode, and output data high at default is to power

down internal PHY and other external MII device

GPIO1~3 defaults are input ports

O Cable Link Status Output. Active High

This pin is also used as a strap pin to define whether the MII interface is a

reversed MII interface (pulled high) or a normal MII interface (not pulled

high). This pin has a pulled down resistor about 60k ohm internally.

O Issue a wake up signal when wake up event happens

This pin has a pulled down resistor about 60k ohm internally.

I Power on Reset

Active low signal to initiate the DM9000

The DM9000 is ready after 5us when this pin deasserted

Not Connect

P Digital VDD

P Digital GND

Final

10

Version: DM9000-DS-F03

April 23, 2009

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