DM9161CI Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.
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DM9161CI Datasheet PDF : 47 Pages
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DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
5.5 Bias and Clock
Pin No.
Pin Name
47
BGRESG
48
BGRES
42
XT2
43
XT1
5.6 Power
Pin No.
1,2,9
5
6
46
23,30
41
15,33,44
Pin Name
AVDD18
AGND
AGND
AGND
DVDD33
VDD33
DGND
I/O
Description
P Band gap Ground
O Band gap Voltage Reference Resistor 6.8K ohm +/- 1%
I/O Crystal Output; REF_CLK input for RMII mode
I Crystal Input
I/O
Description
P Analog 1.8V Regulator Power output
P Analog Receive Ground
P Analog Transmit Ground
P Analog Substrate Ground
P Digital Power
P Digital Power for Crystal
P Digital Ground
5.7 Table a (Media Type Selection)
OP2
OP1
OP0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Function
Dual Speed 100/10 HDX
Reserved
Reserved
Manually Select 10TX HDX
Manually Select 10TX FDX
Manually Select 100TX HDX
Manually Select 100TX FDX
Auto-negotiation Enables All Capabilities
5.8 Pin Maps of Normal MII, Reduced MII, and 10Base-T GPSI (7-Wired) Mode
Normal MII Mode
TXD [0:1]
TXD [2:3]
TXEN
TXER/TXD [4]
TXCLK
RXD [0:1]
RXD[2:3]
RXER/RXD[4]/RPTR/NODE
RXDV
RXCLK
12
Reduced MII Mode
TXD [0:1]
NC
TXEN
NC
NC
RXD [0:1]
NC
RPTR/NODE
CRS DV
NC
10Base-T GPSI (7-Wired) Mode
TXD [0] ; TXD [1] = NC
NC
TXEN
NC
TXCLK
RXD [0] ; RXD [1] = NC
NC
RPTR/NODE
NC
RXCLK
Final
Version: DM9161CI-DS-F01
February 22, 2012
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