DS2167 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated
Número de pieza
componentes Descripción
Lista de partido
DS2167 Datasheet PDF : 15 Pages
| |||
DS2167/DS2168
CODEC/FILTER HARDWARE MODE INTERCONNECT Figure 2
TRANSMIT FRAME SYNC
TRANSMIT DATA CLOCK
-5.0 V
TRANSMIT
ANALOG
INTERFACE
RECEIVE
ANALOG
INTERFACE
VCC
MCLKX
VBB
DX
GNDA
FSX
TSX
VFXI+
VFSI-
GSX
BCLKX
DR
FSR
BCLK/
CLKSEL
MCLK/PDN
VFRO
RECEIVE DATA CLOCK
RECEIVE FRAME SYNC
POWER ON RESET
(DS1231)
RST
SCLK
XIN
FSX
CLKX
YOUT
FSY
CLKY
SPS
TM0
TM1
VSS
VDD
A0
A5
A2
XOUT
YIN
A3
A4
A1
SDI
CS
MCLK
TP3054 (µ-LAW)
TP3057 (µ-LAW)
TRANSMIT DATA
RECEIVE DATA
POWER DOWN
ACTIVE
10 MHz CLOCK
NOTE:
Suggested Codec/Filters
TP305X
National Semiconductor
ETC505X SGS–Thomson Microelectronics
MC1455XX Motorola
TCM29CXX Texas Instruments
HD44238C Hitachi
*other generic Codec/Filter devices can be substituted.
SOFTWARE MODE
Tying SPS high enabled the software mode. In this
mode, a host microcontroller writes configuration data
to the DS2167/DS2168 serial port via inputs SCLK, SDI,
and CS. Independent control and timeslot registers es-
tablish operating characteristics for the X-side and Y-
side PCM interfaces.
ADDRESS/COMMAND BYTE
In the software mode, the address/command byte is the
first byte written to the serial port; it identifies which of 64
possible ADPCM processors sharing the port wiring is
to be updated. Address data must match that at inputs
A0–A5. If no match occurs, the device ignores the fol-
lowing configuration data. If an address match occurs,
the next three bytes written are accepted as control, in-
put and output timeslot data. Bit ACB.6 determines
which side (X or Y) of the device is to be updated.
CONTROL REGISTER
The control register establishes idle, algorithm reset,
bypass, data format and channel coding for the selected
PCM interface.
The X and Y side PCM interfaces may be independently
disabled (output tri-stated) via IPD; when IPD is set for
022698 5/15
Share Link: 