DS2174Q Ver la hoja de datos (PDF) - Maxim Integrated
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DS2174Q Datasheet PDF : 24 Pages
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DS2174
2. PARALLEL CONTROL INTERFACE
Access to the registers is provided through a nonmultiplexed parallel port. The data bus is 8 bits wide; the
address bus is 4 bits wide. Control registers are accessed directly; memory for long repetitive patterns is
accessed indirectly. RCLK and TCLK are used to update counters and for all rising edge bits in the
register map (RSYNC, LC, TL, SBE). At slow clock rates, sufficient time must be allowed for these port
operations.
Table 2-1. REGISTER MAP
ADDRESS
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
REGISTER NAME
Control Register 1
Control Register 2
Control Register 3
Control Register 4
Status Register
Tap/Seed Register 0
Tap/Seed Register 1
Tap/Seed Register 2
Tap/Seed Register 3
TEST Register
Count Register 0
Count Register 1
Count Register 2
Count Register 3
Count Register 4
Count Register 5
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