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DS2174Q

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Maxim Integrated 

DS2174

1.5 Clock Discussion

There are two methods for moving test patterns through a telecom network.

1) The clock applied to TCLK and RCLK can be gapped by other devices on the target system. The

gapped clock would be applied to TCLK and RCLK only during the appropriate times. TDATn

outputs remain active during clock gaps.

2) The clock applied to TCLK and RCLK can be continuous at the applicable line rate and the

TCLK_EN and RCLK_EN pins can be asserted and deasserted during the appropriate time slots.

TDATn outputs remain active even when TCLK_EN is pulled low. The output level remains static at

the level of the last bit transmitted (output high for a 1, output low for a 0).

1.6 Power-Up Sequence

On power-up, the registers in the DS2174 are in a random state. The user must program all the internal

registers to a known state before proper operation can be ensured.

Figure 1-1. BLOCK DIAGRAM

CR1.5

LC

BIT COUNTER

ERROR COUNTER

SYNC

CR1.0

TL

PATTERN DETECTOR

2n - 1

REPETITIVE PATTERN

GENERATOR

PARALLEL CONTROL PORT

ERROR INSERTION

CS RD WR A[3:0] D[7:0]

RECEIVE

RATE

CONTROL

RCLK_EN

RCLK

RDAT[7:0]

TRANSMIT

RATE

CONTROL

TCLK_EN

TCLK

TDAT[7:0]

TCLK0

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