EBD11UD8ABDA-7A Ver la hoja de datos (PDF) - Elpida Memory, Inc

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EBD11UD8ABDA-7A

1GB DDR SDRAM SO DIMM

Elpida Memory, Inc 

EBD11UD8ABDA

DC Characteristics 1 (TA = 0 to 70°C, VDD = 2.5V ± 0.2V, VSS = 0V)

Parameter

Symbol Grade

max.

Unit Test condition

Notes

Operating current (ACTV-PRE) IDD0

Operating current

(ACTV-READ-PRE)

Idle power down standby

current

Floating idle standby current

IDD1

IDD2P

IDD2F

Quiet idle standby current

Active power down

standby current

Active standby current

Operating current

(Burst read operation)

Operating current

(Burst write operation)

Auto refresh current

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

Self refresh current

Operating current

(4 banks interleaving)

IDD6

IDD7A

-6B

-7A, -7B

-6B

-7A, -7B

-6B

-7A, -7B

-6B

-7A, -7B

-6B

-7A, -7B

-6B

-7A, -7B

-6B

-7A, -7B

-6B

-7A, -7B

1760

1560

2000

1760

48

640

560

400

320

1120

960

2240

1920

2240

1920

2880

2640

64

4000

3440

mA

CKE ≥ VIH,

tRC = tRC (min.)

1, 2, 9

CKE ≥ VIH, BL = 4,

mA CL = 2.5,

1, 2, 5

tRC = tRC (min.)

mA CKE ≤ VIL

4

mA

CKE ≥ VIH, /CS ≥ VIH,

DQ, DQS, DM = VREF

4, 5

mA

CKE ≥ VIH, /CS ≥ VIH,

DQ, DQS, DM = VREF

4, 10

mA CKE ≤ VIL

3

mA

CKE ≥ VIH, /CS ≥ VIH

tRAS = tRAS (max.)

3, 5, 6

mA

CKE ≥ VIH, BL = 2,

CL = 2.5

1, 2, 5, 6

mA

CKE ≥ VIH, BL = 2,

CL = 2.5

1, 2, 5, 6

mA

tRFC = tRFC (min.),

Input ≤ VIL or ≥ VIH

mA

Input ≥ VDD – 0.2 V

Input ≤ 0.2 V

mA BL = 4

5, 6, 7

Notes. 1. These IDD data are measured under condition that DQ pins are not connected.

2. One bank operation.

3. One bank active.

4. All banks idle.

5. Command/Address transition once per one cycle.

6. Data/Data mask transition twice per one cycle.

7. 4 banks active. Only one bank is running at tRC = tRC (min.)

8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.

9. Command/Address transition once every two clock cycles.

10. Command/Address stable at ≥ VIH or ≤ VIL.

DC Characteristics 2 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)

Parameter

Symbol

min.

max.

Unit

Test condition

Input leakage current

ILI

–32

32

Output leakage current

ILO

–10

10

Output high current

IOH

–15.2

—

Output low current

IOL

15.2

—

Note: 1. DDR SDRAM component specification.

µA

VDD ≥ VIN ≥ VSS

µA

VDD ≥ VOUT ≥ VSS

mA

VOUT = 1.95V

mA

VOUT = 0.35V

Notes

1

1

Data Sheet E0287E70 (Ver. 7.0)

11

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