EBE10RD4AEFA-6E-E Ver la hoja de datos (PDF) - Elpida Memory, Inc

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EBE10RD4AEFA-6E-E

1GB Registered DDR2 SDRAM DIMM

Elpida Memory, Inc 

EBE10RD4AEFA-6

Pin Description

Pin name

Function

Address input

A0 to A13

Row address

A0 to A13

Column address A0 to A9, A11

A10 (AP)

Auto precharge

BA0, BA1

Bank select address

DQ0 to DQ63

Data input/output

CB0 to CB7

Check bit (Data input/output)

/RAS

Row address strobe command

/CAS

Column address strobe command

E/WE

Write enable

/CS0

Chip select

CKE0

Clock enable

CK0

Clock input

O/CK0

Differential clock input

DQS0 to DQS17, /DQS0 to /DQS17

Input and output data strobe

SCL

Clock input for serial PD

SDA

Data input/output for serial PD

L SA0 to SA2

Serial address input

VDD

Power for internal circuit

VDDSPD

Power for serial EEPROM

VREF

Input reference voltage

P VSS

Ground

ODT0

/RESET

Par_In*2

r Err_Out*2

ODT control

Reset pin (forces register and PLL inputs low) *1

Parity bit for the address and control bus

Parity error found on the address and control bus

NC

No connection

o Note: 1. Reset pin is connected to both OE of PLL and reset to register.

2. NC/Err_Out (Pin No. 55) and NC/Par_In (Pin No. 68) are for optional function to check address and

duct command parity.

Data Sheet E0740E11 (Ver. 1.1)

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