EBE10RD4AEFA-6E-E Ver la hoja de datos (PDF) - Elpida Memory, Inc

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EBE10RD4AEFA-6E-E

1GB Registered DDR2 SDRAM DIMM

Elpida Memory, Inc 

EBE10RD4AEFA-6

Differential Clock Net Wiring (CK0, /CK0)

0ns (nominal)

SDRAM

PLL

CK0

EOL /CK0

120Ω

IN

OUT1

120Ω

OUT'N'

Feedback in

C

Feedback out

120Ω

SDRAM

Register 1

C

120Ω

Register 2

Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl

be set to 0ns (nominal).

2. Input, output and feedback clock lines are terminated from line to line as shown, and not

from line to ground.

P 3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired

in a similar manner.

4. Termination resistors for the PLL feedback path clocks are located as close to the

roduct input pin of the PLL as possible.

Data Sheet E0740E11 (Ver. 1.1)

9

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