EBE10RD4AEFA-6 Ver la hoja de datos (PDF) - Elpida Memory, Inc
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EBE10RD4AEFA-6 Datasheet PDF : 22 Pages
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EBE10RD4AEFA-6
Serial PD Matrix*1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
128 bytes
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
256 bytes
2
Memory type
0
3
Number of row address
0
4
Number of column address
0
5
Number of DIMM ranks
0
6
Module data width
0
E7
Module data width continuation
0
8
Voltage interface level of this assembly 0
9
DDR SDRAM cycle time, CL = 5
0
10
SDRAM access from clock (tAC)
0
O11
DIMM configuration type
0
12
Refresh rate/type
1
13
Primary SDRAM width
0
L 14
Error checking SDRAM width
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
08H
0EH
0BH
60H
48H
00H
05H
30H
45H
02H
82H
04H
04H
DDR2 SDRAM
14
11
1
72
0
SSTL 1.8V
3.0ns*1
0.45ns*1
ECC
7.8µs
×4
×4
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
P /CAS latency
0 0 1 1 1 0 0 0 38H
DIMM Mechanical Characteristics
0 0 0 0 0 0 0 1 01H
DIMM type information
0 0 0 0 0 0 0 1 01H
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
r SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
o Minimum clock cycle time at CL = 4 0 0 1 1 1 1 0 1 3DH
Maximum data access time (tAC) from
clock at CL = 4
0
1
0
1
0
0
0
0
50H
Minimum clock cycle time at CL = 3 0 1 0 1 0 0 0 0 50H
d Maximum data access time (tAC) from
clock at CL = 3
0
1
1
0
0
0
0
0
60H
Minimum row precharge time (tRP) 0 0 1 1 1 1 0 0 3CH
Minimum
u (tRRD)
row
active
to
row
active
delay
0
0
0
1
1
1
1
0
1EH
Minimum /RAS to /CAS delay (tRCD) 0 0 1 1 1 1 0 0 3CH
Minimum active to precharge time
(tRAS)
0 0 1 0 1 1 0 1 2DH
c Module rank density
0 0 0 0 0 0 0 1 01H
Address and command setup time
before clock (tIS)
0 0 1 0 0 0 0 0 20H
Address and command hold time after
t clock (tIH)
0
0
1
0
1
0
0
0
28H
0
4,8
4
3, 4, 5
4.00mm max.
Registered
Normal
Weak Driver 50Ω
ODT Support
3.75ns*1
0.5ns*1
5.0ns*1
0.6ns*1
15ns
7.5ns
15ns
45ns
1GB
0.20ns*1
0.28ns*1
34
Data input setup time before clock
(tDS)
0 0 0 1 0 0 0 0 10H
0.10ns*1
Data Sheet E0740E11 (Ver. 1.1)
5
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