EM78808 Ver la hoja de datos (PDF) - ELAN Microelectronics
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EM78808 Datasheet PDF : 63 Pages
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R5 page1
SDO
Master Device
SPIR register
SPIW register
EM78808
8-bit Micro-controller
SDI
Salve Device
SDI
SPIS Reg
Bit7
Bit 0
SCK
SDO
SPI module
SCK
Fig.6 Single SPI Master / Salve Communication
Bit 0 ~ Bit 2 (SBR0 ~ SBR2) : SPI baud rate selection bits
SBR2
0
0
0
0
1
1
1
1
SBR1
0
0
1
1
0
0
1
1
SBR0
0
1
0
1
0
1
0
1
Mode
Master
Master
Master
Master
Master
Master
Slave
Baud rate
Fsco
Fsco/2
Fsco/4
Fsco/8
Fsco/16
Fsco/32
X
<Note> Fsco = CPU instruction clock
For example :
If PLL enable and RA PAGE0 (Bit5,Bit4)=(1,1), instruction clock is 3.58MHz/2 Fsco=3.5862MHz/2
If PLL enable and RA PAGE0 (Bit5,Bit4)=(0,0), instruction clock is 0.895MHz/2 Fsco=0.895MHz/2
If PLL disable, instruction clock is 32.768kHz/2 Fsco=32.768kHz/2.
Bit 3 (SCES) : SPI clock edge selection bit
1 Data shifts out on falling edge, and shifts in on rising edge. Data is hold during the high level.
0 Data shifts out on rising edge, and shifts in on falling edge. Data is hold during the low level.
Bit 4 (SE) : SPI shift enable bit
1 Start to shift, and keep on 1 while the current byte is still being transmitted.
0 Reset as soon as the shifting is complete, and the next byte is ready to shift.
<Note> This bit has to be reset in software.
Bit 5 (SRO) : SPI read overflow bit
1 A new data is received while the previous data is still being hold in the SPIB register. In this situation, the
data in SPIS register will be destroyed. To avoid setting this bit, users had better to read SPIB register even if the
transmission is implemented only.
0 No overflow
<Note> This can only occur in slave mode.
Bit 6 (SPIE) : SPI enable bit
1 Enable SPI mode
0 Disable SPI mode
Bit 7 (RBF) : SPI read buffer full flag
1 Receive is finished, SPIB is full.
0 Receive is not finish yet, SPIB is empty.
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* This specification is subject to change without notice.
8/1/2004 (V3.1)
15
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