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ENC28J60-I/SS
(Rev.:2012)

Stand-Alone Ethernet Controller with SPI Interface

Microchip Technology 

ENC28J60

3.0 MEMORY ORGANIZATION

All memory in the ENC28J60 is implemented as static

RAM. There are three types of memory in the

ENC28J60:

• Control Registers

• Ethernet Buffer

• PHY Registers

The Control registers’ memory contains the registers

that are used for configuration, control and status

retrieval of the ENC28J60. The Control registers are

directly read and written to by the SPI interface.

The Ethernet buffer contains transmit and receive

memory used by the Ethernet controller in a single

memory space. The sizes of the memory areas are

programmable by the host controller using the SPI

interface. The Ethernet buffer memory can only be

accessed via the read buffer memory and write buffer

memory SPI commands (see Section 4.2.2 “Read

Buffer Memory Command” and Section 4.2.4 “Write

Buffer Memory Command”).

The PHY registers are used for configuration, control

and status retrieval of the PHY module. The registers

are not directly accessible through the SPI interface;

they can only be accessed through Media Independent

Interface Management (MIIM) implemented in the

MAC.

Figure 3-1 shows the data memory organization for the

ENC28J60.

FIGURE 3-1:

ECON1<1:0>

= 00

= 01

= 10

= 11

ENC28J60 MEMORY ORGANIZATION

Bank 0

Control Registers

00h

Buffer Pointers in Bank 0

19h

1Ah

Common

1Fh

Registers

00h

Ethernet Buffer

0000h

Bank 1

19h

1Ah

1Fh

00h

Common

Registers

Bank 2

19h

1Ah

1Fh

00h

Common

Registers

Bank 3

19h

1Ah

1Fh

Common

Registers

PHY Registers

1FFFh

00h

1Fh

Note: Memory areas are not shown to scale. The size of the control memory space has been scaled to show detail.

 2006-2012 Microchip Technology Inc.

.

DS39662E-page 11

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