ENC28J60-I/SS(2012) Ver la hoja de datos (PDF) - Microchip Technology
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ENC28J60-I/SS Datasheet PDF : 102 Pages
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ENC28J60
3.1 Control Registers
The Control registers provide the main interface
between the host controller and the on-chip Ethernet
controller logic. Writing to these registers controls the
operation of the interface, while reading the registers
allows the host controller to monitor operations.
The Control register memory is partitioned into four
banks, selectable by the bank select bits, BSEL<1:0>,
in the ECON1 register. Each bank is 32 bytes long and
addressed by a 5-bit address value.
The last five locations (1Bh to 1Fh) of all banks point to a
common set of registers: EIE, EIR, ESTAT, ECON2 and
ECON1. These are key registers used in controlling and
monitoring the operation of the device. Their common
mapping allows easy access without switching the bank.
The ECON1 and ECON2 registers are discussed later in
this section.
Some of the available addresses are unimplemented.
Any attempts to write to these locations are ignored
while reads return ‘0’s. The register at address 1Ah in
each bank is reserved; read and write operations
should not be performed on this register. All other
reserved registers may be read, but their contents must
not be changed. When reading and writing to registers
which contain reserved bits, any rules stated in the
register definition should be observed.
Control registers for the ENC28J60 are generically
grouped as ETH, MAC and MII registers. Register
names starting with “E” belong to the ETH group.
Similarly, registers names starting with “MA” belong to
the MAC group and registers prefixed with “MI” belong
to the MII group.
TABLE 3-1: ENC28J60 CONTROL REGISTER MAP
Bank 0
Address
Name
Bank 1
Address
Name
Bank 2
Address
00h
ERDPTL
00h
EHT0
00h
01h
ERDPTH
01h
EHT1
01h
02h
EWRPTL
02h
EHT2
02h
03h
EWRPTH
03h
EHT3
03h
04h
ETXSTL
04h
EHT4
04h
05h
ETXSTH
05h
EHT5
05h
06h
ETXNDL
06h
EHT6
06h
07h
ETXNDH
07h
EHT7
07h
08h
ERXSTL
08h
EPMM0
08h
09h
ERXSTH
09h
EPMM1
09h
0Ah
ERXNDL
0Ah
EPMM2
0Ah
0Bh
ERXNDH
0Bh
EPMM3
0Bh
0Ch ERXRDPTL
0Ch
EPMM4
0Ch
0Dh ERXRDPTH
0Dh
EPMM5
0Dh
0Eh ERXWRPTL
0Eh
EPMM6
0Eh
0Fh ERXWRPTH
0Fh
EPMM7
0Fh
10h
EDMASTL
10h
EPMCSL
10h
11h
EDMASTH
11h
EPMCSH
11h
12h
EDMANDL
12h
—
12h
13h
EDMANDH
13h
—
13h
14h EDMADSTL
14h
EPMOL
14h
15h EDMADSTH
15h
EPMOH
15h
16h
EDMACSL
16h
Reserved
16h
17h
EDMACSH
17h
Reserved
17h
18h
—
18h
ERXFCON
18h
19h
—
19h
EPKTCNT
19h
1Ah
Reserved
1Ah
Reserved
1Ah
1Bh
EIE
1Bh
EIE
1Bh
1Ch
EIR
1Ch
EIR
1Ch
1Dh
ESTAT
1Dh
ESTAT
1Dh
1Eh
ECON2
1Eh
ECON2
1Eh
1Fh
ECON1
1Fh
ECON1
1Fh
Name
MACON1
Reserved
MACON3
MACON4
MABBIPG
—
MAIPGL
MAIPGH
MACLCON1
MACLCON2
MAMXFLL
MAMXFLH
Reserved
Reserved
Reserved
—
Reserved
Reserved
MICMD
—
MIREGADR
Reserved
MIWRL
MIWRH
MIRDL
MIRDH
Reserved
EIE
EIR
ESTAT
ECON2
ECON1
Bank 3
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Name
MAADR5
MAADR6
MAADR3
MAADR4
MAADR1
MAADR2
EBSTSD
EBSTCON
EBSTCSL
EBSTCSH
MISTAT
—
—
—
—
—
—
—
EREVID
—
—
ECOCON
Reserved
EFLOCON
EPAUSL
EPAUSH
Reserved
EIE
EIR
ESTAT
ECON2
ECON1
DS39662E-page 12
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2006-2012 Microchip Technology Inc.
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