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GS71108AJ

128K x 8 1Mb Asynchronous SRAM

Unspecified 

GS71108ATP/J/SJ/U

Write Cycle

Parameter

Write cycle time

Address valid to end of write

Chip enable to end of write

Data set up time

Data hold time

Write pulse width

Address set up time

Write recovery time (WE)

Write recovery time (CE)

Output Low Z from end of write

Write to output in High Z

-7

-8

-10

-12

Symbol

Unit

Min Max Min Max Min Max Min Max

tWC

7

—

8

—

10

—

12

—

ns

tAW

5

—

5.5

—

7

—

8

—

ns

tCW

5

—

5.5

—

7

—

8

—

ns

tDW

3

—

4

—

5

—

6

—

ns

tDH

0

—

0

—

0

—

0

—

ns

tWP

5

—

5.5

—

7

—

8

—

ns

tAS

0

—

0

—

0

—

0

—

ns

tWR

0

—

0

—

0

—

0

—

ns

tWR1

0

—

0

—

0

—

0

—

ns

tWLZ*

3

—

3

—

3

—

3

—

ns

tWHZ*

—

3

—

3.5

—

4

—

5

ns

* These parameters are sampled and are not 100% tested

Rev: 1.04a 10/2002

7/14

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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