GS881E18BD(2002) Ver la hoja de datos (PDF) - Giga Semiconductor
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GS881E18BD Datasheet PDF : 34 Pages
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GS881E18B(T/D)/GS881E32B(D)/GS881E36B(T/D)
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
L
LBO
H
Linear Burst
Interleaved Burst
Output Register Control
L
FT
H or NC
Flow Through
Pipeline
Power Down Control
L or NC
ZZ
H
Active
Standby, IDD = ISB
Note:
There is a are pull-up devices on the ZQ, SCD FT pin and a pull-down devices on the PE and ZZ pins, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.00b 12/2002
10/34
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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