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HEF4027B Datasheet PDF : 13 Pages
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NXP Semiconductors
HEF4027B
Dual JK flip-flop
11. Dynamic characteristics
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Extrapolation formula[1] Min Typ Max Unit
tPHL
HIGH to LOW
CP → Q, Q;
5V
propagation delay see Figure 4
10 V
78 ns + (0.55 ns/pF)CL
-
29 ns + (0.23 ns/pF)CL
-
105 210 ns
40 80 ns
15 V
22 ns + (0.16 ns/pF)CL
-
30 60 ns
CD → Q;
see Figure 4
5V
10 V
93 ns + (0.55 ns/pF)CL
-
33 ns + (0.23 ns/pF)CL
-
120 240 ns
45 90 ns
15 V
27 ns + (0.16 ns/pF)CL
-
35 70 ns
SD → Q;
see Figure 4
5V
10 V
113 ns + (0.55 ns/pF)CL
-
44 ns + (0.23 ns/pF)CL
-
140 280 ns
55 110 ns
15 V
32 ns + (0.16 ns/pF)CL
-
40 80 ns
tPLH
LOW to HIGH
CP → Q, Q;
5V
propagation delay see Figure 4
10 V
58 ns + (0.55 ns/pF)CL
-
27 ns + (0.23 ns/pF)CL
-
85 170 ns
35 70 ns
15 V
22 ns + (0.16 ns/pF)CL
-
30 60 ns
CD → Q;
see Figure 4
5V
10 V
48 ns + (0.55 ns/pF)CL
-
24 ns + (0.23 ns/pF)CL
-
75 150 ns
35 70 ns
15 V
17 ns + (0.16 ns/pF)CL
-
25 50 ns
SD → Q;
see Figure 4
5V
10 V
43 ns + (0.55 ns/pF)CL
-
19 ns + (0.23 ns/pF)CL
-
70 140 ns
30 60 ns
15 V
17 ns + (0.16 ns/pF)CL
-
25 50 ns
tt
transition time
see Figure 4
5V
[2] 10 ns + (1.00 ns/pF)CL
-
60 120 ns
10 V
9 ns + (0.42 ns/pF)CL
-
30 60 ns
15 V
6 ns + (0.28 ns/pF)CL
-
20 40 ns
tsu
set-up time
J, K → CP;
see Figure 5
5V
10 V
50 25 -
ns
30 10 -
ns
15 V
20
5-
ns
th
hold time
J, K → CP;
see Figure 5
5V
10 V
25
0-
ns
20
0-
ns
15 V
15
5-
ns
tW
pulse width
CP LOW;
minimum width
see Figure 5
5V
10 V
15 V
80 40 -
ns
30 15 -
ns
24 12 -
ns
SD, CD HIGH;
minimum width
see Figure 6
5V
10 V
15 V
90 45 -
ns
40 20 -
ns
30 15 -
ns
trec
recovery time
SD, CD inputs; 5 V
see Figure 6
10 V
+20 −15 -
ns
+15 −10 -
ns
15 V
+10 −5 -
ns
HEF4027B_5
Product data sheet
Rev. 05 — 10 November 2008
© NXP B.V. 2008. All rights reserved.
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