HI5667 Ver la hoja de datos (PDF) - Intersil
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HI5667 Datasheet PDF : 10 Pages
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HI5667
TABLE 1. A/D CODE TABLE
OFFSET BINARY OUTPUT CODE
(DFS LOW)
TWO’S COMPLEMENT OUTPUT CODE
(DFS HIGH)
CODE CENTER
DESCRIPTION
+Full Scale (+FS) -7/16 LSB
+FS - 17/16 LSB
+9/16 LSB
-7/16 LSB
-FS + 19/16 LSB
-Full Scale (-FS) + 9/16 LSB
NOTE:
DIFFERENTIAL M
LM
L
INPUT
S
SS
S
VOLTAGE
B
BB
B
(VIN+ - VIN-) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
0.498291V
1111111101111111
0.494385V
1111111101111111
2.19727mV
1000000000000000
-1.70898V
0111111111111111
-0.493896V
0000000010000000
-0.497803V
0000000010000000
8. The voltages listed above represent the ideal center of each output code shown with VREFIN = +2.5V.
Digital Output Control and Clock Requirements
The HI5667 provides a standard high-speed interface to
external TTL logic families.
In order to ensure rated performance of the HI5667, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL levels.
Performance of the HI5667 will only be guaranteed at
conversion rates above 1MSPS. This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1MSPS will have to be
performed before valid data is available.
A Data Format Select (DFS) pin is provided which will
determine the format of the digital data outputs. When at
logic low, the data will be output in offset binary format.
When at logic high, the data will be output in two’s
complement format. Refer to Table 1 for further information.
The output enable pin, OE, when pulled high will three-state
the digital outputs to a high impedance state. Set the OE
input to logic low for normal operation.
OE INPUT
0
1
DIGITAL DATA OUTPUTS
Active
High Impedance
Supply and Ground Considerations
The HI5667 has separate analog and digital supply and ground
pins to keep digital noise out of the analog signal path. The
digital data outputs also have a separate supply pin, DVCC2 ,
which can be powered from a 3.0V or 5.0V supply. This allows
the outputs to interface with 3.0V logic if so desired.
The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the HI5667 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply should be isolated with a
ferrite bead from the digital supply.
Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
Static Performance Definitions
Offset Error (VOS)
The midscale code transition should occur at a level 1/4 LSB
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input that
is 3/4 LSB below Positive Full Scale (+FS) with the offset
error removed. Full scale error is defined as the deviation of
the actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Power Supply Sensitivity
Each of the power supplies are moved plus and minus 5% and
the shift in the offset and full scale error (in LSBs) is noted.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the HI5667. A low distortion sine
wave is applied to the input, it is coherently sampled, and the
output is stored in RAM. The data is then transformed into the
frequency domain with an FFT and analyzed to evaluate the
9
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