HSP50214 Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Lista de partido
HSP50214 Datasheet PDF : 54 Pages
| |||
HSP50214
CIC Gain Calculations
The gain through the CIC filter increases with increased dec-
imation. The programmable barrel shifter that precedes the
first integrator in the CIC is used to offset this variation. Gain
variations due to decimation should be offset using the 4-bit
CIC Shift Gain word. This allows the input signal level to be
adjusted in 6dB steps to control the CIC output level.
The gain at each stage of the CIC is:
k = RN,
(EQ. 6)
where R is the decimation factor and N is the number of stages.
The input to the CIC from the mixer is 15 bits, and the bit widths
of the accumulators for the five stages in the HSP50214 are 40,
36, 32, 32, and 32, as shown in Figure 16. This limits the maxi-
mum decimation in the CIC to 32 for a full scale input.
If R is 32, the gain through all five integrator stages is 325 = 225.
(The gain through the last four CIC stages it is 220, through the
last 3 it is 215, etc.) The sum of the input bits and the growth
bits cannot exceed the accumulator size. This means that for a
decimation of 32 and 15 input bits, the first accumulator must
be 15 + 25 = 40 bits.
Thus the value of the CIC Shift Gain word can be calculated:
(EQ. 7)
NOTE: The number of input bits is IIN. (If the number of bits into
the CIC filter used the value 40 replaces 39).
For 14 bits, Equation 7 becomes:
SG = FLOOR[25 – log2(R)5 ]for 4 < R < 32
= 15
for R = 4
(EQ. 8A)
For 12 bits, Equation 7 becomes:
SG = FLOOR[27 – log2(R)5 ]for 5 < R < 40
= 15
for 4 ≤ R ≤ 5
(EQ. 8B)
For 10 bits, Equation 7 becomes:
SG = FLOOR[29 – log2(R)5 ]for 6 < R < 52
= 15
for 4 ≤ R ≤ 6
(EQ. 8C)
For 8 bits, Equation 7 becomes:
SG = FLOOR[31 – log2(R)5 ]for 9 < R < 64
= 15
for 4 ≤ R ≤ 9
(EQ. 8D)
Figure 15 is plot of Equations 8A through 8D. The 4-bit CIC
Shift Gain word has a range from 0 to 15. The 6-bit Decima-
tion Rate Register, (R-1), has a range from 0 to 63, limited by
the input resolution as cited above.
Using the Input Gain Adjust Control Signals
The input gain offset control GAINADJ(2:0)) is provided to offset
the signal gain through the part, i.e. to keep the CIC filter output
level constant as the analog front end attenuation is changed.
The gain adjust offset is 6dB per code, so the gain adjust range is
0 to 42dB. For example, if 12dB of attenuation is switched in at
the receiver RF front end, a code of 2 would increase the gain at
the input to the CIC filter up 12dB so that the CIC filter output
would not drop by 12dB. This fixed gain adjust eliminates the
need for the software to continually normalize.
One must, exercise care when using this function as it can
cause overflow in the CIC filter. Each gain adjust in the
shifter from the gain adjust control signals is the equivalent
of an extra bit of input. The maximum decimation in the CIC
is reduced accordingly. With a decimation of 32, all 40 bits of
the CIC are needed, so no input offset gain is allowed. As
the decimation is reduced, the allowable offset gain
increases. Table 3 shows the decimation range versus
desired offset gain range. Table 3 assumes that the CIC Shift
Gain has been programmed per Equation 7 or 8A.
The CIC filter decimation counter can be loaded synchronous
with other PDC chips, using the SYNCIN1 signal and the CIC
External Sync Enable bit. The CIC external Sync Enable is set
via Control Word 0, bit 19.
0
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
0
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
0
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
2-32
2-33
2-34
2-35
2-36
2-37
2-38
2-39
0
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
2-32
2-33
2-34
2-35
0
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
0
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
0
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
0
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
FIGURE 16. CIC FILTER BIT WEIGHTING
NOTE: If 14 input bits are not needed, the gain adjust can be in-
creased by one for each bit that the input is shifted down
at the input. For example, if only 12 bits are needed, an
offset range of 24dB is possible for a decimation of 24.
14
Share Link: 