HT1647A Ver la hoja de datos (PDF) - Holtek Semiconductor
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HT1647A Datasheet PDF : 19 Pages
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PATENTED
HT1647A
Symbol
Parameter
Test Conditions
VDD
Conditions
Min. Typ. Max. Unit
fCLK2 4-Bit Data Clock (RD Pin)
3V
Duty cycle 50%
5V
¾
¾
75 kHz
¾
¾
150 kHz
tCS
4-Bit Interface Reset Pulse Width
(Figure 3)
¾ CS
¾ 250
¾
ns
Write mode
3V
Read mode
tCLK
WR, RD Input Pulse Width (Figure 1)
Write mode
5V
Read mode
3.34
¾
¾
ms
6.67
1.67
¾
¾
ms
3.34
tr, tf
Rise/Fall Time Serial Data Clock 3V
Width (Figure 1)
5V
¾
¾ 120
¾
ns
tsu
Setup Time for DB to WR, RD Clock 3V
Width (Figure 2)
5V
¾
¾ 120
¾
ns
th
Hold Time for DB to WR, RD Clock 3V
Width (Figure 2)
5V
¾
¾ 120
¾
ns
tsu1
Setup Time for CS to WR, RD Clock 3V
Width (Figure 3)
5V
¾
¾ 100
¾
ns
th1
Hold Time for CS to WR, RD Clock 3V
Width (Figure 3)
5V
¾
¾ 100
¾
ns
tOFF
VDD OFF Times (Figure 4)
¾ VDD drop down to 0V
20
¾
¾
ms
tSR
VDD Rising Slew Rate (Figure 4)
¾¾
0.05 ¾
¾ V/ms
Note:
1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal
Power-on Reset (POR) circuit will not operate normally.
2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions
of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for
20ms (min.) before rising to the normal operating voltage.
V A L ID D A T A
V DD
tf
tr
DB
50%
W R ,R D 90%
C lo c k
50%
10%
V DD
GND
ts u
th
GND
tC L K
tC L K
W R ,R D
50%
C lo c k
GND
Figure 1
Figure 2
tC S
V DD
CS
50%
GND
ts u 1
th 1
W R ,R D
C lo c k
50%
V DD
GND
F ir s t C lo c k
L a s t C lo c k
Figure 3
VDD
0V
tS R
tO F F
Figure 4. Power-on Reset Timing
Rev. 1.40
7
April 29, 2011
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