Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
DC CHARACTERISTICS II (TA= 0 to 70oC)
Parameter
Symbol
Test Condition
Speed
Unit Note
567H
Operating Current
IDD1
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
120 110 100 100 mA 1
Precharge Standby Cur- IDD2P
rent
in Power Down Mode IDD2PS
CKE ≤ VIL(max), tCK = 15ns
CKE ≤ VIL(max), tCK = ∞
2
mA
2
mA
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Precharge Standby Cur- IDD2N
rent
in Non Power Down
Input signals are changed one time during
2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
18
mA
Mode
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
15
Active Standby Current IDD3P CKE ≤ VIL(max), tCK = 15ns
in Power Down Mode IDD3PS CKE ≤ VIL(max), tCK = ∞
3
mA
3
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Active Standby Current IDD3N
Input signals are changed one time during
2clks.
40
in Non Power Down
All other pins ≥ VDD-0.2V or ≤ 0.2V
mA
Mode
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
35
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
120 110 100 100 mA 1
Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active
170 160 150 150 mA 2
Self Refresh Current
IDD6
CKE ≤ 0.2V
Normal
1
mA
3
Low power
400
uA
Super Low
power
300
uA 3, 4
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. HY57V641620ET(P) Series: Normal Power
HY57V641620ELT(P) Series: Low Power
HY57V641620EST(P) Series: Super Low Power
Rev. 1.5 / Feb. 2005
9