ICS9248-136 Ver la hoja de datos (PDF) - Integrated Circuit Systems

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ICS9248-136

Frequency Generator & Integrated Buffers for K7 Processor

Integrated Circuit Systems 

ICS9248-136

Advance Information

Byte 6: Control , Active/Inactive Register

(1= enable, 0 = disable)

BIT PIN# PWD

DESCRIPTION

Bit7 2,3 0 REF strength 0=1X, 1=2X

Bit6 45

CPUCLKT1 - Stop - Control

0 0=CPU_STOP# will control CPUCLKT1,

1=CPUCLKT1 is free running even if CPU_STOP# is low

Bit5 -

X AGPSEL (Readback)

Bit4 -

X MODE (Readback)

Bit3 -

X CPU_STOP# (Readback)

Bit2 -

X PCI_STOP# (Readback)

Bit1 -

X SDRAM_STOP# (Readback)

Bit0 -

AGP Speed Toggle

1 0=AGPSEL (pin2) will be determined by latch input setting,

1=AGPSEL will be opposite of latch input setting

Byte 7: Vendor ID Register

(1= enable, 0 = disable)

BIT

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PIN#

-

-

-

-

-

-

-

-

PWD

DESCRIPTION

0 Reserved

0 Reserved

1 Reserved

0 Reserved

1 Reserved

0 Reserved

0 Reserved

0 Reserved

Third party brands and names are the property of their respective owners.

6

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