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ICSSSTUAF32866C

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Integrated Device Technology 

ICSSSTUAF32866C

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Logic Diagram (1:2)

COMMERCIAL TEMPERATURE GRADE

G2

RESET

CLK H1

J1

CLK

D1 - D6,

D8 - D13

11

A3, T3

VREF

C1 G5

PAR_IN G1

LPS0

(Internal Node)

D CCEE

CLK Q

R

11 D1 - D6,

D8 - D13

Parity

Check

D1 - D6,

D8 - D13

11

0

DQ

1

CLK

R

D

Q

CLK

R

CE

1

D

Q0

CLK

R

11 Q1A - Q6A,

Q8A - Q13A

11 Q1B - Q6B,

Q8B - Q13B

A2 PPO

D2 QERR

G6

C0

CLK

2-Bit

Counter

R

LPS1

(Internal Node)

0

D

Q

1

CLK

R

Parity Logic Diagram for 1:2 Register - B Configuration (Positive Logic);

C0 = 1, C1 = 1

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

10

ICSSSTUAF32866C

7100/9

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