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ICSSSTUAF32866C

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Integrated Device Technology 

ICSSSTUAF32866C

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

COMMERCIAL TEMPERATURE GRADE

Functional Block Diagram for 1:2 Mode (Positive Logic)

RESET

CLK

CLK

VREF

DCKE

1D

C1

R

DODT

1D

C1

R

DCS

1D

C1

R

QCKEA

QCKEB(1)

QODTA

QODTB (1)

QCSA

(1)

QCSB

CSR

D1

0

1

1D

C1

R

Q1A

(1)

Q1B

TO 10 OTHER CHANNELS (D2-D6, D8-D10, D12-D13)

NOTE:

1. Disabled in 1:1 configuration.

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

3

ICSSSTUAF32866C

7100/9

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