8405202QA Ver la hoja de datos (PDF) - Intersil
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8405202QA Datasheet PDF : 37 Pages
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80C86
AC Electrical Specifications
VCC = 5.0V ±10%; TA = 0°C to +70°C (C80C86, C80C86-2)
VCC = 5.0V ±100%; TA = -55°C to +125°C (M80C86)
VCC = 5.0V ±5%; TA = -55°C to +125°C (M80C86-2). Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Continued)
SYMBOL
PARAMETER
TEST
CONDITIONS
80C86
MIN
MAX
80C86-2
MIN
MAX
UNITS
(23) TCLLH ALE Active Delay
CL = 100pF
80
50
ns
(24) TCHLL ALE Inactive Delay
CL = 100pF
85
55
ns
(25) TLLAX Address Hold Time to ALE Inactive CL = 100pF
TCHCL - 10
TCHCL - 10
ns
(26) TCLDV Data Valid Delay
CL = 100pF
10
110
10
60
ns
(27) TCLDX2 Data Hold Time
CL = 100pF
10
10
ns
(28) TWHDX Data Hold Time After WR
CL = 100pF
TCLCL - 30
TCLCL - 30
ns
(29) TCVCTV Control Active Delay 1
CL = 100pF
10
110
10
70
ns
(30) TCHCTV Control Active Delay 2
CL = 100pF
10
110
10
60
ns
(31) TCVCTX Control Inactive Delay
CL = 100pF
10
110
10
70
ns
(32) TAZRL Address Float to READ Active
CL = 100pF
0
0
ns
(33) TCLRL RD Active Delay
CL = 100pF
10
165
10
100
ns
(34) TCLRH RD Inactive Delay
CL = 100pF
10
150
10
80
ns
(35) TRHAV RD Inactive to Next Address Active
CL = 100pF
TCLCL - 45
TCLCL - 40
ns
(36) TCLHAV HLDA Valid Delay
CL = 100pF
10
160
10
100
ns
(37) TRLRH RD Width
CL = 100pF
2TCLCL - 75
2TCLCL - 50
ns
(38) TWLWH WR Width
CL = 100pF
2TCLCL - 60
2TCLCL - 40
ns
(39) TAVAL Address Valid to ALE Low
CL = 100pF
TCLCH - 60
TCLCH - 40
ns
(40) TOLOH Output Rise Time
From 0.8V to 2.0V
20
15
ns
(41) TOHOL Output Fall Time
From 2.0V to 0.8V
20
15
ns
NOTES:
8. Signal at 82C84A shown for reference only.
9. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
10. Applies only to t2 state (8ns into t3).
19
FN2957.3
January 9, 2009
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