IDT72265LA Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT72265LA

CMOS SUPERSYNC FIFO 8,192 x 18 16,384 x 18

Integrated Device Technology 

IDT72255LA/72265LA SUPERSYNC FIFO™

8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

RCLK

tENS

tENH

tRTS

Q0 - Qn

Wx

WCLK

tRTS

tENS

1

tSKEW2

1

Wx+1

2

tENH

tREF

tHF

2

3

4

tENH

tENH

tA

W1 (4)

tA

W2

W3

tPAE

tREF (5)

tPAF

4670 drw 15

NOTES:

1. Retransmit setup is complete after OR returns LOW.

2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the

Retransmit setup procedure. D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA.

3. OE = LOW

4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.

5. OR goes LOW at 60 ns + 2 RCLK cycles + tREF.

Figure 12. Retransmit Timing (FWFT Mode)

WCLK

tENS

tLDS

tENH

tLDH

tENH

tLDH

tDS

SI

BIT 0

EMPTY OFFSET

NOTE:

1. X = 12 for the IDT72255LA and X = 13 for the IDT72265LA.

BIT X (1)

BIT 0

FULL OFFSET

tDH

BIT X (1)

4670 drw 16

Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)

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