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IDT72805LB

CMOS DUAL SyncFIFO DUAL 256 x 18 DUAL 512 x 18 DUAL 1,024 x 18 DUAL 4,096 x 18

Integrated Device Technology 

IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFOTM

256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WCLK

WEN

PAF

tCLKH

tCLKL

tENS (1)

tENH

D - (m + 1) words in FIFO

tPAFA

D - m words in FIFO D - (m + 1) words in FIFO

RCLK

REN

tENS

tPAFA

NOTES:

1. m = PAF offset.

2. D = maximum FIFO Depth.

In IDT Standard Mode: D = 256 for the IDT72805, 512 for the IDT72815, 1,024 for the IDT72825 and 4,096 for the IDT72845.

In FWFT Mode: D = 257 for the IDT72805, 513 for the IDT72815, 1,025 for the IDT72825 and 4,097 for the IDT72845.

3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.

4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.

3139 drw 14

Figure 14. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)

WCLK

WEN

HF

RCLK

REN

tCLKH

tCLKL

tENS

D/2 words in FIFO(2),

[ ] D-1

2

+

1

words in FIFO(3)

tENH

tHF

D/2 + 1 words in FIFO(2),

[ ] D-1

2 +2

words in FIFO(3)

tHF

tENS

NOTES:

1. D = maximum FIFO Depth.

In IDT Standard Mode: D = 256 for the IDT72805, 512 for the IDT72815, 1,024 for the IDT72825 and 4,096 for the IDT72845.

In FWFT Mode: D = 257 for the IDT72805, 513 for the IDT72815, 1,025 for the IDT72825 and 4,097 for the IDT72845.

2. For IDT Standard Mode.

3. For FWFT Mode.

4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during Reset.

Figure 15. Half-Full Flag Timing (IDT Standard and FWFT Modes)

16

D/2 words in FIFO(2),

[ ] D-1

2 +1

words in FIFO(3)

3139 drw 15

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