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IDT72815LB35BG

CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1024 x 18

Integrated Device Technology 

IDT72805/72815/72825 CMOS Dual SyncFIFO™

256 x 18, 512 x 18, and 1024 x 18

WCLK

D0 - D17

NO WRITE

tSKEW1 (1)

tDS

t WFF

FF

DATA WRITE

t WFF

WEN

COMMERCIAL TEMPERATURE RANGE

NO WRITE

tSKEW1

(1)

t DS

DATA WRITE

tWFF

RCLK

REN

tENS

tENH

tENS

t ENH

OE

LOW

tA

tA

Q0 - Q17 DATA IN OUTPUT REGISTER

DATA READ

NEXT DATA READ

3139 drw 11

NOTE:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the

time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.

Figure 8. Full Flag Timing

5.17

12

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