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IDT72V845

3.3 VOLT CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18

Integrated Device Technology 

IDT72V805/72V815/72V825/72V835/72V845

3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18

WCLK

D0 - D17

FF

NO WRITE

1

tSKEW1(1)

2

tDS

tWFF

Wd

tWFF

WEN

RCLK

REN

tENS

tENH

OE LOW

tA

Q0 - Q17

DATA IN OUTPUT REGISTER

DATA READ

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

NO WRITE

1

tSKEW1(1)

2

tDS

DATA WRITE

tWFF

tENS

tENH

tA

NEXT DATA READ

4295 drw 24

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising

edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion time may be delayed an extra WCLK cycle.

2. LD = HIGH.

3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.

Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)

WCLK

D0 - D17

WEN

FF

RCLK

REN

tCLKH

1

tCLK

tCLKL

tSKEW1(1)

2

tDS

tDH

DATAIN VALID

tENS

tENH

tWFF

tWFF

NO OPERATION

4295 drw 25

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising

edge of RCLK and the rising edge of WCLK is less than tSKEW1. then the FF deassertion may be delayed an extra WCLK cycle.

2. LD = HIGH

3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.

Figure 25. Write Cycle Timing with Double Register-Buffered FF (IDT Standard Mode)

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