IDT72V3622 Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT72V3622
Integrated Device Technology
IDT72V3622 Datasheet PDF : 29 Pages
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IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3622/72V3632/72V3642 with
CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x ICC(f) + Σ(CL x VCC2 X fo)
N
where:
N
=
CL
=
fo
=
number of outputs = 36
output capacitance load
switching frequency of an output
200
175
150
125
100
75
50
25
0
0
fdata = 1/2 fS
TA = 25οC
CL = 0 pF
VCC = 3.3V
VCC = 3.6V
VCC = 3.0V
10
20
30
40
50
60
70
80
90
100
fS Clock Frequency MHz
4660 drw 03a
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
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