IDT82V3352 Ver la hoja de datos (PDF) - Integrated Device Technology

Número de pieza

componentes Descripción

Lista de partido

IDT82V3352

SYNCHRONOUS ETHERNET WAN PLL

Integrated Device Technology 

IDT82V3352

SYNCHRONOUS ETHERNET WAN PLL

DESCRIPTION

The IDT82V3352 is an integrated, single-chip solution for the Syn-

chronous Equipment Timing Source for Stratum 3, SMC, 4E and 4

clocks in SONET / SDH equipments, DWDM and Wireless base station,

such as GSM, 3G, DSL concentrator, Router and Access Network appli-

cations.

The device supports three types of input clock sources: recovered

clock from STM-N or OC-n, PDH network synchronization timing and

external synchronization reference timing.

The T0 path supports three primary operating modes: Free-Run,

Locked and Holdover. In Free-Run mode, the DPLL refers to the master

clock. In Locked mode, the DPLL locks to the selected input clock. In

Holdover mode, the DPLL resorts to the frequency data acquired in

Locked mode. Whatever the operating mode is, the DPLL gives a stable

performance without being affected by operating conditions or silicon

process variations.

If the DPLL outputs are processed by T0/T4 APLL, the outputs of the

device will be in a better jitter/wander performance.

The device provides programmable DPLL bandwidths: 0.1 Hz to 560

Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different set-

tings cover all SONET / SDH clock synchronization requirements.

A high stable input is required for the master clock in different appli-

cations. The master clock is used as a reference clock for all the internal

circuits in the device. It can be calibrated within ±741 ppm.

All the read/write registers are accessed through a serial micropro-

cessor interface. The device supports Serial microprocessor interface

mode only.

The device can be used typically in Chapter 3.17 Line Card Applica-

tion.

Description

8

March 23, 2009

Share Link: