IDT82V3385 Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT82V3385 Datasheet PDF : 145 Pages
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IDT82V3385
SYNCHRONOUS ETHERNET WAN PLL
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 32
3.10.1.5 Holdover Mode ................................................................................................................................................................. 33
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 33
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 33
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 33
3.10.1.5.4 Manual ........................................................................................................................................................... 33
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 33
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 33
3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 33
3.10.2.1 Free-Run Mode ................................................................................................................................................................ 33
3.10.2.2 Locked Mode .................................................................................................................................................................... 33
3.10.2.3 Holdover Mode ................................................................................................................................................................. 34
3.11 T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 35
3.11.1 PFD Output Limit ............................................................................................................................................................................ 35
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 35
3.11.3 PBO (T0 only) ................................................................................................................................................................................. 35
3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 35
3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 35
3.11.5.1 T0 Path ............................................................................................................................................................................. 35
3.11.5.2 T4 Path ............................................................................................................................................................................. 36
3.12 T0 / T4 APLL ................................................................................................................................................................................................. 37
3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 37
3.13.1 Output Clocks ................................................................................................................................................................................. 37
3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 41
3.14 MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 43
3.15 INTERRUPT SUMMARY ............................................................................................................................................................................... 44
3.16 T0 AND T4 SUMMARY ................................................................................................................................................................................. 44
3.17 POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 45
4 TYPICAL APPLICATION ................................................................................................................................................. 46
4.1 MASTER / SLAVE APPLICATION ............................................................................................................................................................... 46
5 MICROPROCESSOR INTERFACE .................................................................................................................................. 47
5.1 EPROM MODE .............................................................................................................................................................................................. 47
5.2 MULTIPLEXED MODE .................................................................................................................................................................................. 48
5.3 INTEL MODE ................................................................................................................................................................................................. 51
5.4 MOTOROLA MODE ...................................................................................................................................................................................... 53
5.5 SERIAL MODE .............................................................................................................................................................................................. 55
6 JTAG ................................................................................................................................................................................ 57
7 PROGRAMMING INFORMATION .................................................................................................................................... 58
7.1 REGISTER MAP ............................................................................................................................................................................................ 58
7.2 REGISTER DESCRIPTION ........................................................................................................................................................................... 63
7.2.1 Global Control Registers ............................................................................................................................................................... 63
7.2.2 Interrupt Registers ......................................................................................................................................................................... 72
7.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 76
7.2.4 Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 87
7.2.5 T0 / T4 DPLL Input Clock Selection Registers ............................................................................................................................. 97
7.2.6 T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 101
7.2.7 T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 103
7.2.8 Output Configuration Registers .................................................................................................................................................. 116
7.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 121
7.2.10 Synchronization Configuration Registers ................................................................................................................................. 122
8 THERMAL MANAGEMENT ........................................................................................................................................... 124
8.1 JUNCTION TEMPERATURE ...................................................................................................................................................................... 124
8.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 124
Table of Contents
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May 14, 2010
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