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IDT82V3385

SYNCHRONOUS ETHERNET WAN PLL

Integrated Device Technology 

List of Tables

Table 1: Pin Description ............................................................................................................................................................................................. 13

Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 18

Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 18

Table 4: Pre-Divider Function .................................................................................................................................................................................... 20

Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 22

Table 6: Input Clock Selection for T0 Path ................................................................................................................................................................ 23

Table 7: Input Clock Selection for T4 Path ................................................................................................................................................................ 23

Table 8: External Fast Selection ................................................................................................................................................................................ 23

Table 9: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 24

Table 10: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 25

Table 11: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 25

Table 12: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 26

Table 13: Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 27

Table 14: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 28

Table 15: T0 DPLL Operating Mode Control ............................................................................................................................................................... 29

Table 16: T4 DPLL Operating Mode Control ............................................................................................................................................................... 31

Table 17: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 31

Table 18: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 32

Table 19: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 33

Table 20: Holdover Frequency Offset Read ................................................................................................................................................................ 33

Table 21: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 34

Table 22: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 36

Table 23: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 37

Table 24: Outputs on OUT1 ~ OUT5 if Derived from T0/T4 DPLL Outputs ................................................................................................................ 37

Table 25: Outputs on OUT1 ~ OUT5 if Derived from T0 APLL ................................................................................................................................... 38

Table 26: Outputs on OUT2 ~ OUT4 if Derived from T4 APLL ................................................................................................................................... 39

Table 27: Outputs on OUT1 & OUT5 if Derived from T4 APLL ................................................................................................................................... 40

Table 28: Synchronization Control ............................................................................................................................................................................... 41

Table 29: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 42

Table 30: Device Master / Slave Control ..................................................................................................................................................................... 43

Table 31: Related Bit / Register in Chapter 3.15 ......................................................................................................................................................... 44

Table 32: Microprocessor Interface ............................................................................................................................................................................. 47

Table 33: Access Timing Characteristics in EPROM Mode ......................................................................................................................................... 47

Table 34: Read Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 48

Table 35: Write Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 50

Table 36: Read Timing Characteristics in Intel Mode .................................................................................................................................................. 51

Table 37: Write Timing Characteristics in Intel Mode .................................................................................................................................................. 52

Table 38: Read Timing Characteristics in Motorola Mode ........................................................................................................................................... 53

Table 39: Write Timing Characteristics in Motorola Mode ........................................................................................................................................... 54

Table 40: Read Timing Characteristics in Serial Mode ................................................................................................................................................ 55

Table 41: Write Timing Characteristics in Serial Mode ................................................................................................................................................ 56

Table 42: JTAG Timing Characteristics ....................................................................................................................................................................... 57

Table 43: Register List and Map .................................................................................................................................................................................. 58

Table 44: Power Consumption and Maximum Junction Temperature ....................................................................................................................... 124

Table 45: Thermal Data ............................................................................................................................................................................................. 125

Table 46: Absolute Maximum Rating ......................................................................................................................................................................... 126

Table 47: Recommended Operation Conditions ........................................................................................................................................................ 126

Table 48: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 127

List of Tables

6

May 14, 2010

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