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INT5130CS

Integrated Powerline MAC/PHY Transceiver

Unspecified 

INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet

Functional Description

The interfaces that provide data, status, and control to and from the INT5130 include…

• External host interface provided via the Media Independent Interface (MII) format (described by

IEEE802.3u, Clause 22) or a General Purpose Serial Interface (GPSI).

• Management control provided via the Management Data Interface (MDI) or the Serial Peripheral Interface

(SPI).

• Analog Front End interface.

• LEDs indicating network status.

• Optional E2PROM interface providing a path to initialize the INT5130 with PowerPacket-specific

configuration information.

• The JTAG port implements the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.

LEDS

MDI

or SPI

Config

Regs

MII or

GPSI

MII/GPSII

Interface

ROM RAM

RISC uProcessor

Core

Link

Sequencer

PHY

Seq

Interface

DMA

Arbiter

PHY

DMA

FIFOs

PHY

Core

AFE

Logic

ADIO(9:0)

AGC(7:0)

TEST

JTAG

E2PROM

SPI

Master

Interface Block

Buffer

RAM

PowerPacket MAC

PowerPacket PHY

Figure 1: INT5130 Block Diagram

INTELLON CONFIDENTIAL

10

Rev 8.1

ADVANCE INFORMATION

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