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INT5130CS

Integrated Powerline MAC/PHY Transceiver

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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet

The INT5130 implements Intellon’s patented PowerPacket OFDM technology and is fully compliant with the

HomePlug Powerline Alliance Industry Specification v1.0. Specifically tailored to reliably deliver up to 14

Mbps over the difficult powerline communication environment, the INT5130 combats deep attenuation notches,

noises sources, and multi-path fading by allocating usable frequencies according to the signal to noise ratio

(SNR). Synchronization is achieved in low SNR channels without the use of pilot carriers. The MAC

implements a CSMA/CA scheme with prioritization and automatic repeat request (ARQ) for reliable delivery of

Ethernet packets via packet encapsulation. Built-in quality-of-service (QoS) features provide the necessary

bandwidth for multimedia payloads including voice, data, audio, and video. Prioritized random access along with

segment bursting minimizes the demands on the receiver resources and maximizes the throughput of the

network while still providing excellent latency response and jitter performance. The INT5130’s contention-free

access capability extends this concept of segment bursting to allow the transmission of multiple frames over

the powerline without relinquishing the control of the medium. Utilizing contention-free access, a single station

may act as a controller for the entire network.

System designers have the option of embedding PowerPacket-specific control information within the packet

stream for optimal control and performance or may choose to provide this information via the separate

E2PROM interface. Providing this configuration and control information through a separate E2PROM interface

allows the system designer to leverage standard Ethernet drivers.

The INT5130 operates on both 2.5V and 3.3V supplies, offers 5V I/O tolerance, and is packaged in a 144-pin

LQFP. Intellon offers a complete solution for powerline communication applications by providing the INT5130 in

conjunction with the INT1000 Analog Conversion IC.

Functional Block Diagram

INT5130

RESET

PowerPacket MAC

Interface Block

MDIO Control

MDCLK/MDIO

- OR -

SPI Control

SDI,SDO,SCLK,CS

MDI/SPI

Select

MII

RX[3:0],RXCLK,RXDV,RX_ER

TX[3:0],TXCLK,TXEN,TX_ER

COL,CRS

- OR -

GPSI

RXD,RXCLK,RXEN

TXD,TXCLK,TXEN

COL,TXBSY

Config

Regs

MII/GPSI

Interface

ROM

RAM

RISC

uProc

Core

Arbiter

DMA

&

Link

Sequencer

MII/GPSI

Select

Buffer

RAM

JTAG

Control

JTAG

Port

PowerPacket PHY

PHY

Core

AFE

Interface

Configuration

EEPROM

Control

CLK IN

E2PROM

Control

LED

Control

Power

&

GND

Gain

Control

ADC

DAC

IFace

MDIO

Address

Select

LEDs

CLK OUT

INTELLON CONFIDENTIAL

2

Rev 8.1

ADVANCE INFORMATION

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