IS61LV2568L-10KI(2005) Ver la hoja de datos (PDF) - Integrated Silicon Solution

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IS61LV2568L-10KI
(Rev.:2005)

256K x 8 HIGH-SPEED CMOS STATIC RAM

Integrated Silicon Solution 

IS61LV2568L

ISSI ®

WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)

Symbol

tWC

tSCE

tAW

tHA

tSA

tPWE1

tPWE2

tSD

tHD

tHZWE(3)

tLZWE(3)

Parameter

Write Cycle Time

CE to Write End

Address Setup Time to Write End

Address Hold from Write End

Address Setup Time

WE Pulse Width (OE = HIGH)

WE Pulse Width (OE = LOW)

Data Setup to Write End

Data Hold from Write End

WE LOW to High-Z Output

WE HIGH to Low-Z Output

- 8 ns

Min. Max

8—

7—

7—

0—

0—

6—

6.5 —

4—

0—

—3

0—

-10 ns

Min. Max.

10 —

8—

8—

0—

0—

7—

8—

5—

0—

—4

0—

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

8

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. C

07/25/05

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