datasheetbank_Logo
búsqueda de Hoja de datos y gratuito Fichas de descarga

ISL8002(2013_01) Ver la hoja de datos (PDF) - Intersil

Número de pieza
componentes Descripción
Lista de partido
ISL8002
(Rev.:2013_01)
Intersil
Intersil Intersil
ISL8002 Datasheet PDF : 22 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
ISL8002, ISL8002A, ISL80019, ISL80019A
Output Voltage Selection
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage
relative to the internal reference voltage and feed it back to the
inverting input of the error amplifier. Refer to Figure 35.
The output voltage programming resistor, R2, will depend on the
value chosen for the feedback resistor and the desired output
voltage of the regulator. The value for the feedback resistor is
typically between 10kand 100k, as shown in Equation 3.
R1
=
R2
---V----O----
VFB
1⎠⎞
(EQ. 3)
If the output voltage desired is 0.6V, then R2 is left unpopulated
and R1 is shorted. There is a leakage current from VIN to LX. It is
recommended to preload the output with 10µA minimum. For
better performance, add 22pF in parallel with R1. Check loop
analysis before use in application.
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current flowing back to the
battery rail. At least two 22µF X5R or X7R ceramic capacitors are
a good starting point for the input capacitor selection.
Output Capacitor Selection
An output capacitor is required to filter the inductor current.
Output ripple voltage and transient response are 2 critical factors
when considering output capacitance choice. The current mode
control loop allows for the usage of low ESR ceramic capacitors
and thus smaller board layout. Electrolytic and polymer
capacitors may also be used.
Additional consideration applies to ceramic capacitors. While
they offer excellent overall performance and reliability, the actual
in-circuit capacitance must be considered. Ceramic capacitors
are rated using large peak-to-peak voltage swings and with no DC
bias. In the DC/DC converter application, these conditions do not
reflect reality. As a result, the actual capacitance may be
considerably lower than the advertised value. Consult the
manufacturers data sheet to determine the actual in-application
capacitance. Most manufacturers publish capacitance vs DC bias
so that this effect can be easily accommodated. The effects of
AC voltage are not frequently published, but an assumption of
~20% further reduction will generally suffice. The result of these
considerations can easily result in an effective capacitance 50%
lower than the rated value. Nonetheless, they are a very good
choice in many applications due to their reliability and extremely
low ESR.
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
For the ceramic capacitors (low ESR) =
VOUTripple=
-----------------Δ----I-----------------
8FS WCO U T
(EQ. 4)
where ΔI is the inductor’s peak to peak ripple current, FSW is the
switching frequency and COUT is the output capacitor.
If using electrolytic capacitors then:
VOUTripple= ΔI*ESR
(EQ. 5)
Regarding transient response needs, a good starting point is to
determine the allowable overshoot in VOUT if the load is suddenly
removed. In this case, energy stored in the inductor will be
transferred to COUT causing its voltage to rise. After calculating
capacitance required for both ripple and transient needs, choose
the larger of the calculated values. The following equation
determines the required output capacitor value in order to
achieve a desired overshoot relative to the regulated voltage.
COUT
=
-----------------------------------I--O----U----T----2----*---L------------------------------------
VOUT2*(VOUTMAX VOUT)2 1 )
(EQ. 6)
where VOUTMAX/VOUT is the relative maximum overshoot
allowed during the removal of the load. For an overshoot of 5%,
the equation becomes as follows:
COUT = V-----O----U----T--I--2O----*-U--(--T1---.-2-0--*-5--L---2-----–----1-----)
(EQ. 7)
Loop Compensation Design
When COMP is not connected to VDD, the COMP pin is active for
external loop compensation. The ISL8002, ISL8002A, ISL80019,
and ISL80019A use constant frequency peak current mode
control architecture to achieve fast loop transient response. An
accurate current sensing pilot device in parallel with the upper
MOSFET is used for peak current control signal and overcurrent
protection. The inductor is not considered as a state variable
since its peak current is constant, and the system becomes a
single order system. It is much easier to design a type II
compensator to stabilize the loop than to implement voltage
mode control. Peak current mode control has an inherent input
voltage feed-forward function to achieve good line regulation.
Figure 52 shows the small signal model of the synchronous buck
regulator.
^iin
V^in
+
^iL LP
RLP
ILd^ 1:D Vind^
RT
vo^
Rc
Ro
Co
d^
T i(S)
K
Fm
+
He(S)
Tv(S)
v^comp
-Av(S)
FIGURE 52. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
19
FN7888.1
January 7, 2013

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]