ISL8002(2013_01) Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Lista de partido
ISL8002 Datasheet PDF : 22 Pages
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ISL8002, ISL8002A, ISL80019, ISL80019A
VOUT
R1
C4
VFB
-
VREF GM
R2
+
VCOMP
R14
C8
C7
FIGURE 53. TYPE II COMPENSATOR
Figure 53 shows the type II compensator and its transfer function
is expressed as Equation 8:
Av(S)=
v-ˆ---cv-ˆ--oF---m-B----p- =
(---C-----7----+-----C-G---8--M--)---⋅--⋅-(--R-R---2-1-----+-----R----2----)
---⎝⎛---1-----+-----ω---------cS------z------1----⎠⎞---⎝⎛---1-----+------ω--------c-S-----z------2----⎠⎞----
S
⎛
⎝
1
+
ω-----cS---p---1--⎠⎞
⎛
⎝
1
+
ω-----cS---p---2--⎠⎞
(EQ. 8)
where,
ωcz1
=
--------1---------
R14 C7
,
ωcz2
=
-------1------- ,
R1C4
ωcp
1
=
R---C--1---74---C-+----7-C--C--8---8-, ωcp2=
--R----1-----+----R-----2--
C4R1R2
COMPENSATOR DESIGN GOAL
• High DC gain
• Choose Loop bandwidth fc less than 100kHz
• Gain margin: >10dB
• Phase margin: >50°
The compensator design procedure is as follows:
The loop gain at crossover frequency of fc has unity gain.
Therefore, the compensator resistance R14 is determined by
Equation 9.
R14 = -2---π-G---f--Mc---V---⋅-o--V--C--F--o--B--R----t = 26×103 ⋅ fcVoCo
(EQ. 9)
Where GM is the trans-conductance of the voltage error
amplifier.
Compensator capacitors C7 and C8 are then given by
Equations 10 and 11.
C7
=
R-----o---C-----o-
R14
=
-V----o---C-----o--
Io R14
(EQ. 10)
C8= max(-R--R--c--1-C--4---o-,π----f--s--1-R-----1---4-)
(EQ. 11)
An optional zero can boost the phase margin. ωCZ2 is a zero due
to R1 and C4.
Put compensator zero 2 to 5 times fc:
C4=
-------1--------
πfcR1
(EQ. 12)
Example: VIN = 5V, VOUT = 1.8V, IO = 2A, FSW = 1MHz,
R1 = 200kΩ, R2 = 100kΩ, COUT = 2x22µF/3mΩ, L = 2.2µH,
fc = 100kHz, then compensator resistance R14:
R14 = 26×103 ⋅ 100kHz ⋅ 1.8V ⋅ 44μF = 205kΩ
(EQ. 13)
Using the closest standard value for R14 value is fine (200kΩ).
C7
=
1----.--8---V------⋅---4---4----μ----F--
2A ⋅ 200kΩ
=
198 p F
(EQ. 14)
C8= max(-3---m----2--Ω-0---0--⋅--k-4---Ω4----μ----F--,-π----⋅---1----M------H----z-1---(--2----0---0----k---Ω------))= (1pF,2.3pF) (EQ. 15)
The closest standard values for C7 and C8 are also fine. There is
approximately 3pF parasitic capacitance from VCOMP to GND;
Therefore, C8 is optional. Use C7 = 220pF and C8 = OPEN.
C4= π----1----0---0----k---H-----z1-----⋅---2---0---0----k----Ω-- = 16pF
(EQ. 16)
Use C4 = 15pF. Note that C4 may increase the loop bandwidth
from previously estimated value. Figure 54 shows the simulated
voltage loop gain. It is shown that it has 114kHz loop bandwidth
with 52° phase margin and 10dB gain margin. It may be more
desirable to achieve more phase margin. This can be
accomplished by lowering R14 by 20% to 50%.
60
45
30
15
0
-15
-30
100
1k
10k
100k
1M
FREQUENCY (Hz)
180
150
120
90
60
30
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 54. SIMULATED LOOP GAIN
20
FN7888.1
January 7, 2013
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