ISL90841UIV1427Z Ver la hoja de datos (PDF) - Intersil

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ISL90841UIV1427Z

Quad Digitally Controlled Potentiometers (XDCP™)

Intersil 

ISL90841

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

TYP

MIN (NOTE 1)

tF

SDA and SCL fall time

(Note 15)

From 70% to 30% of VCC

20 +

0.1 * Cb

Cb

Capacitive loading of SDA or SCL Total on-chip and off-chip

10

(Note 15)

Rpu

SDA and SCL bus pull-up resistor off- Maximum is determined by tR and tF

1

(Note 15) chip

For Cb = 400pF, max is about 2~2.5kΩ

For Cb = 40pF, max is about 15~20kΩ

tSU:A A1 and A0 setup time

Before START condition

600

tHD:A A1 and A0 hold time

After STOP condition

600

MAX

250

400

SDA vs SCL Timing

tF

tHIGH

tLOW

tR

UNIT

ns

pF

kΩ

ns

ns

SCL

tSU:STA

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

tSU:DAT

tHD:STA

tHD:DAT

tAA tDH

tSU:STO

tBUF

A0 and A1 Pin Timing

SCL

START

SDA IN

A0, A1

tSU:A

CLK 1

STOP

tHD:A

5

FN8094.0

August 1, 2005

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