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LTC1553CG

5-Bit Programmable Synchronous Switching Regulator Controller for Pentium® II Processor

Linear Technology 

LTC1553

APPLICATIONS INFORMATION

Soft Start and Current Limit

The LTC1553 includes a soft start circuit which is used for

initial start-up and during current limit operation. The SS

pin requires an external capacitor to GND with the value

determined by the required soft start time. An internal

10µA current source is included to charge the external SS

capacitor. During start-up, the COMP pin is clamped to a

diode drop above the voltage at the SS pin. This prevents

the error amplifier, ERR, from forcing the loop to maxi-

mum duty cycle. The LTC1553 will begin to operate at low

duty cycle as the SS pin rises above about 1.2V (VCOMP ≈

1.8V). As SS continues to rise, QSS turns off and the error

amplifier begins to regulate the output. The MIN compara-

tor is disabled when soft start is active to prevent it from

overriding the soft start function.

The LTC1553 includes yet another feedback loop to con-

trol operation in current limit. Just before every falling

edge of G1, the current comparator, CC, samples and

holds the voltage drop measured across the external

MOSFET, Q1, at the IFB pin. Note that when VIN = 12V, the

IFB pin requires an external Zener to GND to prevent

voltage transients at the switching node between Q1 and

Q2 from damaging internal structures. CC compares the

voltage at IFB to the voltage at the IMAX pin. As the peak

current rises, the measured voltage across Q1 increases

due to the drop across the RDS(ON) of Q1. When the voltage

at IFB drops below IMAX, indicating that Q1’s drain current

has exceeded the maximum level, CC starts to pull current

out of the external soft start capacitor, cutting the duty

cycle and controlling the output current level. The CC

comparator pulls current out of the SS pin in proportion to

the voltage difference between IFB and IMAX. Under minor

overload conditions, the SS pin will fall gradually, creating

a time delay before current limit takes effect. Very short,

mild overloads may not affect the output voltage at all.

More significant overload conditions will allow the SS pin

to reach a steady state, and the output will remain at a

reduced voltage until the overload is removed. Serious

overloads will generate a large overdrive at CC, allowing it

to pull SS down quickly and preventing damage to the

output components.

By using the RDS(ON) of Q1 to measure the output current,

the current limiting circuit eliminates an expensive dis-

crete sense resistor that would otherwise be required. This

helps minimize the number of components in the high

current path. Due to switching noise and variation of

RDS(ON), the actual current limit trip point is not highly

accurate. The current limiting circuitry is primarily meant

to prevent damage to the power supply circuitry during

fault conditions. The exact current level where the limiting

circuit begins to take effect will vary from unit to unit as the

RDS(ON) of Q1 varies.

For a given current limit level, the external resistor from

IMAX to VIN can be determined by:

( )( ) RIMAX =

ILMAX RDS(ON)Q1

IIMAX

where,

IL MAX

=

ILOAD

+

IRIPPLE

2

ILOAD = Maximum load current

IRIPPLE = Inductor ripple current

( )( ) = VIN − VOUT VOUT

( )( )( ) fOSC LO VIN

fOSC = LTC1553 oscillator frequency = 300kHz

LO = Inductor value

RDS(ON)Q1 = Hot on-resistance of Q1 at ILMAX

IIMAX = Internal 180µA sink current at IMAX

LTC1553

CC

VIN

180µA

IMAX

7

IFB

8

RIMAX

G1

20Ω

G2

Q1

LO

Q2

+

CIN

VOUT

+

COUT

1553 F05

Figure 5. Current Limit Setting

11

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