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LAN9117

High Performance Single-Chip 10/100 Non PCI Ethernet Controller

SMSC -> Microchip 

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

Datasheet

The host bus interface is the primary bus for connection to the embedded host system. This interface

models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.

Programmed I/O transactions are supported.

The LAN9117 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits

wide. The LAN9117 can be interfaced to either Big-Endian or Little-Endian processors.

The host bus data Interface is responsible for host address decoding and data bus steering. The host

bus interface handles the 16 to 32-bit conversion. Additionally, when Big Endian mode is selected, the

data path to the internal controller registers will be reorganized accordingly.

1.11

External MII Interface

The LAN9117 also supports the ability to interface to an external PHY device. This interface is

compatible with all IEEE 802.3 MII compliant physical layer devices. For additional information on the

MII interface and associated signals, please refer to Section 3.12, "MII Interface - External MII

Switching," on page 43 for more information.

SMSC LAN9117

13

DATASHEET

Revision 1.1 (05-17-05)

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