LAN91C110 Ver la hoja de datos (PDF) - SMSC -> Microchip

Número de pieza

componentes Descripción

Lista de partido

LAN91C110

FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications

SMSC -> Microchip 

FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications

Datasheet

S/W DRIVER

packet number command to free up the memory

used by this packet. Remove packet number

from completion FIFO by writing TX INT

Acknowledge Register.

b) Option 1) Release the packet.

Option 2) Check the transmit status in the EPH

STATUS Register, write the packet number of

the current packet to the Packet Number

Register, re-enable TXENA, then go to step 4 to

start the TX sequence again.

MAC SIDE

5.3 Typical Flow of Events for Transmit (Auto Release = 1)

S/W DRIVER

MAC SIDE

1 ISSUE ALLOCATE MEMORY FOR TX - N

BYTES - the MMU attempts to allocate N bytes

of RAM.

2 WAIT FOR SUCCESSFUL COMPLETION

CODE - Poll until the ALLOC INT bit is set or

enable its mask bit and wait for the interrupt.

The TX packet number is now at the Allocation

Result Register.

3 LOAD TRANSMIT DATA - Copy the TX packet

number into the Packet Number Register. Write

the Pointer Register, then use a block move

operation from the upper layer transmit queue

into the Data Register.

4 ISSUE "ENQUEUE PACKET NUMBER TO TX

FIFO" - This command writes the number

present in the Packet Number Register into the

TX FIFO. The transmission is now enqueued.

No further CPU intervention is needed until a

transmit interrupt is generated.

5

The enqueued packet will be transferred to the

MAC block as a function of TXENA (nTCR) bit

and of the deferral process (1/2 duplex mode

only) state.

6

Transmit pages are released by transmit

completion.

7

a) The MAC generates a TXEMPTY interrupt

upon a completion of a sequence of enqueued

packets.

b) If a TX failure occurs on any packets, TX INT

is generated and TXENA is cleared, transmission

sequence stops. The packet number of the

failure packet is presented at the TX FIFO

PORTS Register.

8 a) SERVICE INTERRUPT – Read Interrupt

Status Register, exit the interrupt service

routine.

b) Option 1) Release the packet.

SMSC LAN91C110 Rev. B

Page 38

DATASHEET

Revision 1.0 (11-04-08)

Share Link: