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LAN91C111I-NC

10/100 Non-PCI Ethernet Single Chip MAC + PHY

SMSC -> Microchip 

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

SYM

t42

t43

t44

t45

t46

t47

t48

t49

t50

t51

t52

t53

t54

t55

t56

t57

t58

t59

Table 14.4 Link Pulse Timing Characteristics

PARAMETER

LIMIT

MIN TYP MAX

NLP Transmit Link Pulse Width

See Figure 7.8

NLP Transmit Link Pulse Period

8

24

NLP Receive Link Pulse Width Required 50

For Detection

NLP Receive Link Pulse Minimum Period 6

7

Required For Detection

NLP Receive Link Pulse Maximum

50

150

Period Required For Detection

NLP Receive Link Pulse Required To

3

Exit Link Fail State

3

3

FLP Transmit Link Pulse Width

100

150

FLP Transmit Clock Pulse to Data Pulse 55.5 62.5 69.5

Period

FLP Transmit Clock Pulse to Clock Pulse 111

Period

125 139

FLP Transmit Link Pulse Burst Period 8

22

FLP Receive Link Pulse Width Required 50

For Detection

FLP Receive Link Pulse Minimum Period 5

25

Required For Clock Pulse Detection

FLP Receive Link Pulse Maximum

165

185

Period Required For Clock Pulse

Detection

FLP Receive Link Pulse Minimum Period 15

47

Required For Data Pulse Detection

FLP Receive Link Pulse Maximum

78

100

Period Required For Data Pulse

Detection

FLP Receive Link Pulse Burst Minimum 5

7

Period Required For Detection

FLP Receive Link Pulse Burst Maximum 50

150

Period Required For Detection

FLP Receive Link Pulses Bursts

3

3

3

Required To Detect AutoNegotiation

Capability

UNIT

nS

mS

nS

mS

mS

Link

Pulses

nS

μS

μS

mS

nS

μS

μS

μS

μS

mS

mS

Link

Pulses

CONDITIONS

link_test_min

link_test_max

lc_max

interval_timer

transmit_link_burst_time

r

flp_test_min_timer

flp_test_max_timer

data_detect_min_timer

data_detect_max_timer

nlp_test_min_timer

nlp_test_max_timer

SMSC LAN91C111 REV C

123

DATASHEET

Revision 1.91 (08-18-08)

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