LAN91C95 Ver la hoja de datos (PDF) - SMSC -> Microchip
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LAN91C95 Datasheet PDF : 144 Pages
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POWERDOWN LOGIC
The pins and bits involved in powerdown are:
1. PWRDWN/TXCLK - Input pin valid when XENDEC is not zero (0).
2. Pwrdwn bits in ECSR and MCSR registers - One bit for each function
3. Enable Function bits in ECOR and MCOR registers - One bit for each function
4. PWRDN - Ethernet powerdown bit in Control Register.
5. WAKUP_EN - Magic packet receive enable bit in the Control Register
6. nWAKEUP - Pin for Magic Packet receive + Ethernet function powerdown
Table 6A - ISA MODE Defined States (Refer to table 6B for next states to wake-up events)
(*Rev. C and Higher)
CURRENT STATE
nWAKE
PWRD
WN
Pin(A=
No. Assrtd)
UP-EN
PIN
(A=
Assrtd)
ECOR
FUCNTION
ENABLE
ECSR
POWER
DOWN
CTR
PWRD
WN BIT
1
A
X
X
X
X
CTR
WAKE-
UP_EN
BIT
X
MCOR
FUNC
ENABLE
X
MCSR
POWER
DOWN
X
POWERS
DOWN
Everything.
Asserts the
modem
power
down pin
(nPWDN)
also
DOES
NOT
POWER
DOWN
2
nA
A
X
X
X
X
-
-
Ethernet
Ethernet
Tx
Rx, Link
3
nA
nA
X
0
0
0
-
-
Ethernet
Tx, Rx,
Link
4
nA
nA
X
0
0
1
-
-
Ethernet
Ethernet
0
1
Tx
Rx, Link
5
nA
nA
X
0
1
0
-
-
Ethernet
Tx, Rx,
Link
Note 1: The chart assumes that ECOR Function Enable bit is meaningless in ISA mode.
Note 2: ECSR Power Down bit must not be set to one(1) in ISA mode
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