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LAN91C95

ISA/PCMCIA Full Duplex Single-Chip Ethernet and Modem Controller with RAM

SMSC -> Microchip 

receive are fully independent. It has 6 kbytes of

internal memory and the MMU manages

memory in 256 byte pages. The memory size

accommodates the increase in interrupt latency

resulting from simultaneous LAN and modem

operation as well as the potential for

simultaneous transmit and receive traffice in

some full duplex applications.

The LAN91C95 integrates most of the 802.3

functionality, incorporating the MAC layer

protocol, the physical layer encoding and

decoding functions with the ability to handle the

AUI interface. For twisted pair networks, the

LAN91C95 integrates the twisted pair

transceiver as well as the link integrity test

functions.

Packet reception and transmission are

determined by memory availability. All other

resources are always available if memory is

available. To complement this flexible

architecture, all ISA bus interface functions are

incorporated in the LAN91C95, as well as a 6K

byte packet RAM and serial EEPROM-based

setup. The user can select or modify

configuration choices.

The LAN91C95 is a true 10BASE-T single chip

able to interface a system or a local bus.

Directly-driven LEDs for installation and run-

time diagnostics are provided, as well as 802.3

statistics gathering to facilitate network

management.

The LAN91C95 offers:

The LAN91C95 stores the Configuration High integration:

Information Structure (CIS) on reset or power-up

Single chip adapter including:

from the serial EEPROM. This allows the host

Packet RAM

to access data to allow the setup of the PCMCIA

ISA bus interface

multi-function card.

PCMCIA interface

EEPROM interface

In ISA mode, the serial EEPROM acts as

Encoder decoder with AUI interface

storage for configuration and IEEE Ethernet

Full duplex, magic packet 10BASE-T

address information compatible with the existing

transceiver

LAN9000 family of ISA Ethernet controllers.

Lucent Technologies and Rockwell

International modem interface

In PCMCIA mode, the serial EEPROM stores

the CIS, as well as the IEEE address, High performance:

information, but it does not store any I/O or IRQ

Chained (“back-to-back”) packet handling

information since this information is handled by

with no CPU intervention:

the host’s socket controller. For CIS

Queues transmit packets

requirements above 512 bytes, an optional

Queues receive packets

external parallel EEPROM can be used in

Full duplex operation for higher network

conjunction with the internal CIS. This allows

throughput

additional external, non-volatile storage for

Stores results in memory along with

applications that require XIP and use the

packet

modem function. If the serial EEPROM is not

Queues Ethernet and modem interrupts

used in PCMCIA mode, the parallel EEPROM

Optional single interrupt upon

must be used. In this case, the parallel

completion of transmit chain

EEPROM is selected for the first 512 bytes of

storage as well, allowing the CIS to be stored in Fast block move operation for load/unload:

the parallel EEPROM and, on power-up, to be

CPU sees packet bytes as if stored

read directly by the host. The remaining parallel

contiguously

EEPROM can be used for XIP applications, if

Handles 16 bit transfers regardless of

needed.

address alignment

Access to packet through fixed window

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