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LAN9215I

Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support

SMSC -> Microchip 

1.11

1.12

Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support

Datasheet

Host Bus Interface (SRAM Interface)

The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as

an interface for the LAN9215i Control and Status Registers (CSR’s).

The host bus interface is the primary bus for connection to the embedded host system. This interface

models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.

Programmed I/O transactions are supported.

The LAN9215i host bus interface supports 16-bit bus transfers. Internally, all data paths are 32-bits

wide. The LAN9215i can be interfaced to either Big-Endian or Little-Endian processors.

External MII Interface

The LAN9215i also supports the ability to interface to an external PHY device. This interface is

compatible with all IEEE 802.3 MII compliant physical layer devices. For additional information on the

MII interface and associated signals, please refer to Section 3.11, "MII Interface - External MII

Switching," on page 43 for more information.

Revision 1.93 (12-12-07)

14

DATASHEET

SMSC LAN9215i

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