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LAN8700

±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR™ in a Small Footprint

SMSC -> Microchip 

±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWRTM in a Small Footprint

Datasheet

Table 3.3 Management Signals

SIGNAL NAME

MDIO

MDC

TYPE

I/O

I

DESCRIPTION

Management Data Input/OUTPUT: Serial management data

input/output.

Management Clock: Serial management clock.

Table 3.4 Boot Strap Configuration Inputs (Note 3.1)

SIGNAL NAME

CRS/

PHYAD4

FDUPLEX/

PHYAD3

ACTIVITY/

PHYAD2

LINK/

PHYAD1

SPEED100/

PHYAD0

RXD2/

MODE2

RXD1/

MODE1

RXD0/

MODE0

RX_CLK/

REGOFF

COL/

RMII/

CRS_DV

TYPE

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

DESCRIPTION

PHY Address Bit 4: set the default address of the PHY. This

signal is mux’d with CRS

Note: This signal is mux’d with CRS

PHY Address Bit 3: set the default address of the PHY.

Note: This signal is mux’d with FDUPLEX

PHY Address Bit 2: set the default address of the PHY.

Note: This signal is mux’d with ACTIVITY

PHY Address Bit 1: set the default address of the PHY.

Note: This signal is mux’d with LINK

PHY Address Bit 0: set the default address of the PHY.

Note: This signal is mux’d with SPEED100

PHY Operating Mode Bit 2: set the default MODE of the PHY.

See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 52, for

the MODE options.

Note: This signal is mux’d with RXD2

PHY Operating Mode Bit 1: set the default MODE of the PHY.

See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 52, for

the MODE options.

Note: This signal is mux’d with RXD1

PHY Operating Mode Bit 0: set the default MODE of the PHY.

See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 52, for

the MODE options.

Note: This signal is mux’d with RXD0

Internal Regulator off: disable the internal +1.8v regulator.

This signal is mux’d with RX_CLK.

„ Float to enable the internal +1.8v regulator.

„ Pull up with a resistor (see Table 4.3, “Boot Strapping

Configuration Resistors,” on page 32) to VDDIO to disable the

internal regulator.

Digital Communication Mode: set the digital communications

mode of the PHY to RMII or MII. This signal is muxed with the

Collision signal (MII mode) and Carrier Sense/ receive Data Valid

(RMII mode)

„ Float for MII mode.

„ Pull up with a resistor to VDDIO for RMII mode (see Table 4.3,

“Boot Strapping Configuration Resistors,” on page 32) .

SMSC LAN8700/LAN8700I

15

DATASHEET

Revision 1.0 (02-09-07)

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